Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

9-2 Vol. 1
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
• Chapter 11, “Intel® MMX™ Technology System Programming,” in the Intel® 64
and IA-32 Architectures Software Developer’s Manual, Volume 3B, describes the
manner in which MMX technology is integrated into the IA-32 system
programming model.
9.2 THE MMX TECHNOLOGY PROGRAMMING
ENVIRONMENT
Figure 9-1 shows the execution environment for MMX technology. All MMX instruc-
tions operate on MMX registers, the general-purpose registers, and/or memory as
follows:
• MMX registers — These eight registers (see Figure 9-1) are used to perform
operations on 64-bit packed integer data. They are named MM0 through MM7.
• General-purpose registers — The eight general-purpose registers (see
Figure 3-5) are used with existing IA-32 addressing modes to address operands
in memory. (MMX registers cannot be used to address memory). General-
purpose registers are also used to hold operands for some MMX technology
operations. They are EAX, EBX, ECX, EDX, EBP, ESI, EDI, and ESP.
9.2.1 MMX Technology in 64-Bit Mode and Compatibility Mode
In compatibility mode and 64-bit mode, MMX instructions function like they do in
protected mode. Memory operands are specified using the ModR/M, SIB encoding
described in Section 3.7.5.
Figure 9-1. MMX Technology Execution Environment
0
2
32
-1
Eight 32-Bit
Address Space
General-Purpose
Eight 64-Bit
MMX Registers
Registers