Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 9-7
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
NOTES
The MMX instructions described in this chapter are those instructions
that are available in an IA-32 processor when
CPUID.01H:EDX.MMX[bit 23] = 0.
Section 10.4.4, “SSE 64-Bit SIMD Integer Instructions,” and Section
11.4.2, “SSE2 64-Bit and 128-Bit SIMD Integer Instructions,” list
additional instructions included with SSE/SSE2 extensions that
operate on the MMX registers but are not considered part of the MMX
instruction set.
Table 9-2. MMX Instruction Set Summary
Category Wraparound Signed
Saturation
Unsigned Saturation
Arithmetic Addition
Subtraction
Multiplication
Multiply and Add
PADDB, PADDW,
PADDD
PSUBB, PSUBW,
PSUBD
PMULL, PMULH
PMADD
PADDSB, PADDSW
PSUBSB, PSUBSW
PADDUSB, PADDUSW
PSUBUSB, PSUBUSW
Comparison Compare for Equal
Compare for
Greater Than
PCMPEQB,
PCMPEQW,
PCMPEQD
PCMPGTPB,
PCMPGTPW,
PCMPGTPD
Conversion Pack PACKSSWB,
PACKSSDW
PACKUSWB
Unpack Unpack High
Unpack Low
PUNPCKHBW,
PUNPCKHWD,
PUNPCKHDQ
PUNPCKLBW,
PUNPCKLWD,
PUNPCKLDQ
Packed Full Quadword
Logical And
And Not
Or
Exclusive OR
PAND
PANDN
POR
PXOR
Shift Shift Left Logical
Shift Right Logical
Shift Right
Arithmetic
PSLLW, PSLLD
PSRLW, PSRLD
PSRAW, PSRAD
PSLLQ
PSRLQ