Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 9-15
PROGRAMMING WITH INTEL® MMX™ TECHNOLOGY
9.6.9 Effect of Instruction Prefixes on MMX Instructions
Table 9-3 describes the effect of instruction prefixes on MMX instructions. Unpredict-
able behavior can range from being treated as a reserved operation on one genera-
tion of IA-32 processors to generating an invalid opcode exception on another
generation of processors.
See “Instruction Prefixes” in Chapter 2, “Instruction Format,” of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A, for a description of the
instruction prefixes.
Table 9-3. Effect of Prefixes on MMX Instructions
Prefix Type Effect on MMX Instructions
Address Size Prefix (67H) Affects instructions with a memory operand.
Reserved for instructions without a memory operand and
may result in unpredictable behavior.
Operand Size (66H) Reserved and may result in unpredictable behavior.
Segment Override (2EH, 36H,
3EH, 26H, 64H, 65H)
Affects instructions with a memory operand.
Reserved for instructions without a memory operand and
may result in unpredictable behavior.
Repeat Prefix (F3H) Reserved and may result in unpredictable behavior.
Repeat NE Prefix(F2H) Reserved and may result in unpredictable behavior.
Lock Prefix (F0H) Reserved; generates invalid opcode exception (#UD).
Branch Hint Prefixes (2EH and
3EH)
Reserved and may result in unpredictable behavior.