Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 10-1
CHAPTER 10
PROGRAMMING WITH
STREAMING SIMD EXTENSIONS (SSE)
The streaming SIMD extensions (SSE) were introduced into the IA-32 architecture in
the Pentium III processor family. These extensions enhance the performance of IA-32
processors for advanced 2-D and 3-D graphics, motion video, image processing,
speech recognition, audio synthesis, telephony, and video conferencing.
This chapter describes SSE. Chapter 11, “Programming with Streaming SIMD Exten-
sions 2 (SSE2),” provides information to assist in writing application programs that
use SSE2 extensions. Chapter 12, “Programming with SSE3 and Supplemental
SSE3,” provides this information for SSE3 extensions.
10.1 OVERVIEW OF SSE EXTENSIONS
Intel MMX technology introduced single-instruction multiple-data (SIMD) capability
into the IA-32 architecture, with the 64-bit MMX registers, 64-bit packed integer data
types, and instructions that allowed SIMD operations to be performed on packed
integers. SSE extensions expand the SIMD execution model by adding facilities for
handling packed and scalar single-precision floating-point values contained in
128-bit registers.
If CPUID.01H:EDX.SSE[bit 25] = 1, SSE extensions are present.
SSE extensions add the following features to the IA-32 architecture, while main-
taining backward compatibility with all existing IA-32 processors, applications and
operating systems.
• Eight 128-bit data registers (called XMM registers) in non-64-bit modes; sixteen
XMM registers are available in 64-bit mode.
• The 32-bit MXCSR register, which provides control and status bits for operations
performed on XMM registers.
• The 128-bit packed single-precision floating-point data type (four IEEE single-
precision floating-point values packed into a double quadword).
• Instructions that perform SIMD operations on single-precision floating-point
values and that extend SIMD operations that can be performed on integers:
— 128-bit Packed and scalar single-precision floating-point instructions that
operate on data located in MMX registers
— 64-bit SIMD integer instructions that support additional operations on packed
integer operands located in MMX registers
• Instructions that save and restore the state of the MXCSR register.