Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 10-5
PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
integer operands (see Section 11.2, “SSE2 Programming Environment,” and Section
12.1, “SSE3/SSSE3 Programming Environment and Data types”).
XMM registers can only be used to perform calculations on data; they cannot be used
to address memory. Addressing memory is accomplished by using the general-
purpose registers.
Data can be loaded into XMM registers or written from the registers to memory in
32-bit, 64-bit, and 128-bit increments. When storing the entire contents of an XMM
register in memory (128-bit store), the data is stored in 16 consecutive bytes, with
the low-order byte of the register being stored in the first byte in memory.
10.2.3 MXCSR Control and Status Register
The 32-bit MXCSR register (see Figure 10-3) contains control and status information
for SSE, SSE2, and SSE3 SIMD floating-point operations. This register contains:
• flag and mask bits for SIMD floating-point exceptions
• rounding control field for SIMD floating-point operations
• flush-to-zero flag that provides a means of controlling underflow conditions on
SIMD floating-point operations
• denormals-are-zeros flag that controls how SIMD floating-point instructions
handle denormal source operands
The contents of this register can be loaded from memory with the LDMXCSR and
FXRSTOR instructions and stored in memory with STMXCSR and FXSAVE.
Bits 16 through 31 of the MXCSR register are reserved and are cleared on a power-
up or reset of the processor; attempting to write a non-zero value to these bits, using
either the FXRSTOR or LDMXCSR instructions, will result in a general-protection
exception (#GP) being generated.