Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 10-7
PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
“Rounding,” for a description of the function and encoding of the rounding control
bits.
10.2.3.3 Flush-To-Zero
Bit 15 (FZ) of the MXCSR register enables the flush-to-zero mode, which controls the
masked response to a SIMD floating-point underflow condition. When the underflow
exception is masked and the flush-to-zero mode is enabled, the processor performs
the following operations when it detects a floating-point underflow condition:
• Returns a zero result with the sign of the true result
• Sets the precision and underflow exception flags
If the underflow exception is not masked, the flush-to-zero bit is ignored.
The flush-to-zero mode is not compatible with IEEE Standard 754. The IEEE-
mandated masked response to underflow is to deliver the denormalized result (see
Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”). The flush-to-zero
mode is provided primarily for performance reasons. At the cost of a slight precision
loss, faster execution can be achieved for applications where underflows are common
and rounding the underflow result to zero can be tolerated.
The flush-to-zero bit is cleared upon a power-up or reset of the processor, disabling
the flush-to-zero mode.
10.2.3.4 Denormals-Are-Zeros
Bit 6 (DAZ) of the MXCSR register enables the denormals-are-zeros mode, which
controls the processor’s response to a SIMD floating-point denormal operand condi-
tion. When the denormals-are-zeros flag is set, the processor converts all denormal
source operands to a zero with the sign of the original operand before performing any
computations on them. The processor does not set the denormal-operand exception
flag (DE), regardless of the setting of the denormal-operand exception mask bit
(DM); and it does not generate a denormal-operand exception if the exception is
unmasked.
The denormals-are-zeros mode is not compatible with IEEE Standard 754 (see
Section 4.8.3.2, “Normalized and Denormalized Finite Numbers”). The denormals-
are-zeros mode is provided to improve processor performance for applications such
as streaming media processing, where rounding a denormal operand to zero does
not appreciably affect the quality of the processed data.
The denormals-are-zeros flag is cleared upon a power-up or reset of the processor,
disabling the denormals-are-zeros mode.
The denormals-are-zeros mode was introduced in the Pentium 4 and Intel Xeon
processor with the SSE2 extensions; however, it is fully compatible with the SSE
SIMD floating-point instructions (that is, the denormals-are-zeros flag affects the
operation of the SSE SIMD floating-point instructions). In earlier IA-32 processors
and in some models of the Pentium 4 processor, this flag (bit 6) is reserved. See