Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

10-8 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
Section 11.6.3, “Checking for the DAZ Flag in the MXCSR Register,” for instructions
for detecting the availability of this feature.
Attempting to set bit 6 of the MXCSR register on processors that do not support the
DAZ flag will cause a general-protection exception (#GP). See Section 11.6.6,
“Guidelines for Writing to the MXCSR Register,” for instructions for preventing such
general-protection exceptions by using the MXCSR_MASK value returned by the
FXSAVE instruction.
10.2.4 Compatibility of SSE Extensions with SSE2/SSE3/MMX and
the x87 FPU
The state (XMM registers and MXCSR register) introduced into the IA-32 execution
environment with the SSE extensions is shared with SSE2 and SSE3 extensions.
SSE/SSE2/SSE3 instructions are fully compatible; they can be executed together in
the same instruction stream with no need to save state when switching between
instruction sets.
XMM registers are independent of the x87 FPU and MMX registers, so
SSE/SSE2/SSE3 operations performed on the XMM registers can be performed in
parallel with operations on the x87 FPU and MMX registers (see Section 11.6.7,
“Interaction of SSE/SSE2 Instructions with x87 FPU and MMX Instructions”).
The FXSAVE and FXRSTOR instructions save and restore the SSE/SSE2/SSE3 states
along with the x87 FPU and MMX state.
10.3 SSE DATA TYPES
SSE extensions introduced one data type, the 128-bit packed single-precision
floating-point data type, to the IA-32 architecture (see Figure 10-4). This data type
consists of four IEEE 32-bit single-precision floating-point values packed into a double
quadword. (See Figure 4-3 for the layout of a single-precision floating-point value;
refer to Section 4.2.2, “Floating-Point Data Types,” for a detailed description of the
single-precision floating-point format.)
This 128-bit packed single-precision floating-point data type is operated on in the
XMM registers or in memory. Conversion instructions are provided to convert two
packed single-precision floating-point values into two packed doubleword integers or
Figure 10-4. 128-Bit Packed Single-Precision Floating-Point Data Type
0127
Contains 4 Single-Precision
Floating-Point Values
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