Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

10-20 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
10.4.6.4 SFENCE Instruction
The SFENCE (Store Fence) instruction controls write ordering by creating a fence for
memory store operations. This instruction guarantees that the result of every store
instruction that precedes the store fence in program order is globally visible before
any store instruction that follows the fence. The SFENCE instruction provides an effi-
cient way of ensuring ordering between procedures that produce weakly-ordered
data and procedures that consume that data.
10.5 FXSAVE AND FXRSTOR INSTRUCTIONS
The FXSAVE and FXRSTOR instructions were introduced into the IA-32 architecture in
the Pentium II processor family (prior to the introduction of the SSE extensions). The
original versions of these instructions performed a fast save and restore, respec-
tively, of the x87 FPU register state. (By saving the state of the x87 FPU data regis-
ters, the FXSAVE and FXRSTOR instructions implicitly save and restore the state of
the MMX registers.)
The SSE extensions expanded the scope of these instructions to save and restore the
states of the XMM registers and the MXCSR register, along with the x87 FPU and MMX
state.
The FXSAVE and FXRSTOR instructions can be used in place of the FSAVE/FNSAVE
and FRSTOR instructions; however, the operation of the FXSAVE and FXRSTOR
instructions are not identical to the operation of FSAVE/FNSAVE and FRSTOR.
Table 10-1. PREFETCHh Instructions Caching Hints
PREFETCHh
Instruction Mnemonic Actions
PREFETCHT0 Temporal data—fetch data into all levels of cache hierarchy:
• Pentium III processor—1st-level cache or 2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
PREFETCHT1 Temporal data—fetch data into level 2 cache and higher
• Pentium III processor—2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
PREFETCHT2 Temporal data—fetch data into level 2 cache and higher
• Pentium III processor—2nd-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache
PREFETCHNTA Non-temporal data—fetch data into location close to the processor,
minimizing cache pollution
• Pentium III processor—1st-level cache
• Pentium 4 and Intel Xeon processor—2nd-level cache