Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 10-21
PROGRAMMING WITH STREAMING SIMD EXTENSIONS (SSE)
NOTE
The FXSAVE and FXRSTOR instructions are not considered part
of the SSE instruction group. They have a separate CPUID
feature bit to indicate whether they are present (if
CPUID.01H:EDX.FXSR[bit 24] = 1).
The CPUID feature bit for SSE extensions does not indicate the
presence of FXSAVE and FXRSTOR.
10.6 HANDLING SSE INSTRUCTION EXCEPTIONS
See Section 11.5, “SSE, SSE2, and SSE3 Exceptions,” for a detailed discussion of the
general and SIMD floating-point exceptions that can be generated with the SSE
instructions and for guidelines for handling these exceptions when they occur.
10.7 WRITING APPLICATIONS WITH THE SSE EXTENSIONS
See Section 11.6, “Writing Applications with SSE/SSE2 Extensions,” for additional
information about writing applications and operating-system code using the SSE
extensions.