Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 11-3
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
• Chapter 12, “System Programming for Streaming SIMD Instruction Sets,” in the
Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A,
gives guidelines for integrating the SSE and SSE2 extensions into an operating-
system environment.
11.2 SSE2 PROGRAMMING ENVIRONMENT
Figure 11-1 shows the programming environment for SSE2 extensions. No new
registers or other instruction execution state are defined with SSE2 extensions. SSE2
instructions use the XMM registers, the MMX registers, and/or IA-32 general-purpose
registers, as follows:
• XMM registers — These eight registers (see Figure 10-2) are used to operate on
packed or scalar double-precision floating-point data. Scalar operations are
operations performed on individual (unpacked) double-precision floating-point
values stored in the low quadword of an XMM register. XMM registers are also
used to perform operations on 128-bit packed integer data. They are referenced
by the names XMM0 through XMM7.
• MXCSR register — This 32-bit register (see Figure 10-3) provides status and
control bits used in floating-point operations. The denormals-are-zeros and
flush-to-zero flags in this register provide a higher performance alternative for
the handling of denormal source operands and denormal (underflow) results. For
Figure 11-1. Steaming SIMD Extensions 2 Execution Environment
0
2
32
-1
Eight 32-Bit
32 Bits
EFLAGS Register
Address Space
General-Purpose
Eight 64-Bit
MMX Registers
Eight 128-Bit
XMM Registers
32 Bits
MXCSR Register
Registers