Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

11-4 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
more information on the functions of these flags see Section 10.2.3.4,
“Denormals-Are-Zeros,” and Section 10.2.3.3, “Flush-To-Zero.”
• MMX registers — These eight registers (see Figure 9-2) are used to perform
operations on 64-bit packed integer data. They are also used to hold operands for
some operations performed between MMX and XMM registers. MMX registers are
referenced by the names MM0 through MM7.
• General-purpose registers — The eight general-purpose registers (see
Figure 3-5) are used along with the existing IA-32 addressing modes to address
operands in memory. MMX and XMM registers cannot be used to address
memory. The general-purpose registers are also used to hold operands for some
SSE2 instructions. These registers are referenced by the names EAX, EBX, ECX,
EDX, EBP, ESI, EDI, and ESP.
• EFLAGS register — This 32-bit register (see Figure 3-8) is used to record the
results of some compare operations.
11.2.1 SSE2 in 64-Bit Mode and Compatibility Mode
In compatibility mode, SSE2 extensions function like they do in protected mode. In
64-bit mode, eight additional XMM registers are accessible. Registers XMM8-XMM15
are accessed by using REX prefixes.
Memory operands are specified using the ModR/M, SIB encoding described in Section
3.7.5.
Some SSE2 instructions may be used to operate on general-purpose registers. Use
the REX.W prefix to access 64-bit general-purpose registers. Note that if a REX prefix
is used when it has no meaning, the prefix is ignored.
11.2.2 Compatibility of SSE2 Extensions with SSE, MMX
Technology and x87 FPU Programming Environment
SSE2 extensions do not introduce any new state to the IA-32 execution environment
beyond that of SSE. SSE2 extensions represent an enhancement of SSE extensions;
they are fully compatible and share the same state information. SSE and SSE2
instructions can be executed together in the same instruction stream without the
need to save state when switching between instruction sets.
XMM registers are independent of the x87 FPU and MMX registers; so SSE and SSE2
operations performed on XMM registers can be performed in parallel with x87 FPU or
MMX technology operations (see Section 11.6.7, “Interaction of SSE/SSE2 Instruc-
tions with x87 FPU and MMX Instructions”).
The FXSAVE and FXRSTOR instructions save and restore the SSE and SSE2 states
along with the x87 FPU and MMX states.