Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 11-5
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
11.2.3 Denormals-Are-Zeros Flag
The denormals-are-zeros flag (bit 6 in the MXCSR register) was introduced into the
IA-32 architecture with the SSE2 extensions. See Section 10.2.3.4, “Denormals-Are-
Zeros,” for a description of this flag.
11.3 SSE2 DATA TYPES
SSE2 extensions introduced one 128-bit packed floating-point data type and four
128-bit SIMD integer data types to the IA-32 architecture (see Figure 11-2).
• Packed double-precision floating-point — This 128-bit data type consists of
two IEEE 64-bit double-precision floating-point values packed into a double
quadword. (See Figure 4-3 for the layout of a 64-bit double-precision floating-
point value; refer to Section 4.2.2, “Floating-Point Data Types,” for a detailed
description of double-precision floating-point values.)
• 128-bit packed integers — The four 128-bit packed integer data types can
contain 16 byte integers, 8 word integers, 4 doubleword integers, or 2 quadword
integers. (Refer to Section 4.6.2, “128-Bit Packed SIMD Data Types,” for a
detailed description of the 128-bit packed integers.)
All of these data types are operated on in XMM registers or memory. Instructions are
provided to convert between these 128-bit data types and the 64-bit and 32-bit data
types.
Figure 11-2. Data Types Introduced with the SSE2 Extensions
128-Bit Packed Word Integers
128-Bit Packed Byte Integers
128-Bit Packed Doubleword
Integers
0127
0127
0127
0127
0127
128-Bit Packed Quadword
Integers
128-Bit Packed Double-
Precision Floating-Point
64 63