Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

11-10 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
The ANDNPD (bitwise logical AND NOT of packed double-precision floating-point
values) instruction returns the logical AND NOT of two packed double-precision
floating-point operands.
The ORPD (bitwise logical OR of packed double-precision floating-point values)
instruction returns the logical OR of two packed double-precision floating-point oper-
ands.
The XORPD (bitwise logical XOR of packed double-precision floating-point values)
instruction returns the logical XOR of two packed double-precision floating-point
operands.
11.4.1.4 SSE2 Comparison Instructions
SSE2 compare instructions compare packed and scalar double-precision floating-
point values and return the results of the comparison either to the destination
operand or to the EFLAGS register.
The CMPPD (compare packed double-precision floating-point values) instruction
compares the corresponding values from two packed double-precision floating-point
operands, using an immediate operand as a predicate, and returns a 64-bit mask
result of all 1s or all 0s for each comparison to the destination operand. The value of
the immediate operand allows the selection of any of eight compare conditions:
equal, less than, less than equal, unordered, not equal, not less than, not less than
or equal, or ordered.
The CMPSD (compare scalar double-precision floating-point values) instruction
compares the low values from two packed double-precision floating-point operands,
using an immediate operand as a predicate, and returns a 64-bit mask result of all 1s
or all 0s for the comparison to the low quadword of the destination operand. The
immediate operand selects the compare condition as with the CMPPD instruction.
The COMISD (compare scalar double-precision floating-point values and set EFLAGS)
and UCOMISD (unordered compare scalar double-precision floating-point values and
set EFLAGS) instructions compare the low values of two packed double-precision
floating-point operands and set the ZF, PF, and CF flags in the EFLAGS register to
show the result (greater than, less than, equal, or unordered). These two instruc-
tions differ as follows: the COMISD instruction signals a floating-point invalid-opera-
tion (#I) exception when a source operand is either a QNaN or an SNaN; the
UCOMISD instruction only signals an invalid-operation exception when a source
operand is an SNaN.
11.4.1.5 SSE2 Shuffle and Unpack Instructions
SSE2 shuffle instructions shuffle the contents of two packed double-precision
floating-point values and store the results in the destination operand.
The SHUFPD (shuffle packed double-precision floating-point values) instruction
places either of the two packed double-precision floating-point values from the desti-
nation operand in the low quadword of the destination operand, and places either of