Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture
Vol. 1 2-1
CHAPTER 2
INTEL
®
64 AND IA-32 ARCHITECTURES
The exponential growth of computing power and ownership has made the computer
one of the most important forces shaping business and society. Intel 64 and IA-32
architectures have been at the forefront of the computer revolution and is today the
preferred computer architecture, as measured by computers in use and the total
computing power available in the world.
2.1 BRIEF HISTORY OF INTEL
®
64 AND IA-32
ARCHITECTURE
The following sections provide a summary of the major technical evolutions from
IA-32 to Intel 64 architecture: starting from the Intel 8086 processor to the latest
Intel Core 2 Duo and Intel Xeon processor 5100 series. Object code created for
processors released as early as 1978 still executes on the latest processors in the
Intel 64 and IA-32 architecture families.
2.1.1 16-bit Processors and Segmentation (1978)
The IA-32 architecture family was preceded by 16-bit processors, the 8086 and
8088. The 8086 has 16-bit registers and a 16-bit external data bus, with 20-bit
addressing giving a 1-MByte address space. The 8088 is similar to the 8086 except it
has an 8-bit external data bus.
The 8086/8088 introduced segmentation to the IA-32 architecture. With segmenta-
tion, a 16-bit segment register contains a pointer to a memory segment of up to
64 KBytes. Using four segment registers at a time, 8086/8088 processors are able to
address up to 256 KBytes without switching between segments. The 20-bit
addresses that can be formed using a segment register and an additional 16-bit
pointer provide a total address range of 1 MByte.
2.1.2 The Intel
®
286 Processor (1982)
The Intel 286 processor introduced protected mode operation into the IA-32 archi-
tecture. Protected mode uses the segment register content as selectors or pointers
into descriptor tables. Descriptors provide 24-bit base addresses with a physical
memory size of up to 16 MBytes, support for virtual memory management on a
segment swapping basis, and a number of protection mechanisms. These mecha-
nisms include:
• Segment limit checking