Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

11-18 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
11.4.4.4 Pause
The PAUSE instruction is provided to improve the performance of “spin-wait loops”
executed on a Pentium 4 or Intel Xeon processor. On a Pentium 4 processor, it also
provides the added benefit of reducing processor power consumption while executing
a spin-wait loop. It is recommended that a PAUSE instruction always be included in
the code sequence for a spin-wait loop.
11.4.5 Branch Hints
SSE2 extensions designate two instruction prefixes (2EH and 3EH) to provide branch
hints to the processor (see “Instruction Prefixes” in Chapter 2 of the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 2A). These prefixes can
only be used with the Jcc instruction and only at the machine code level (that is,
there are no mnemonics for the branch hints).
11.5 SSE, SSE2, AND SSE3 EXCEPTIONS
SSE/SSE2/SSE3 extensions generate two general types of exceptions:
• Non-numeric exceptions
• SIMD floating-point exceptions
1
SSE/SSE2/SSE3 instructions can generate the same type of memory-access and
non-numeric exceptions as other IA-32 architecture instructions. Existing exception
handlers can generally handle these exceptions without any code modification. See
“Providing Non-Numeric Exception Handlers for Exceptions Generated by the SSE,
SSE2 and SSE3 Instructions” in Chapter 12 of the Intel® 64 and IA-32 Architectures
Software Developer’s Manual, Volume 3A, for a list of the non-numeric exceptions
that can be generated by SSE/SSE2/SSE3 instructions and for guidelines for handling
these exceptions.
SSE/SSE2/SSE3 instructions do not generate numeric exceptions on packed integer
operations; however, they can generate numeric (SIMD floating-point) exceptions on
packed single-precision and double-precision floating-point operations. These SIMD
floating-point exceptions are defined in the IEEE Standard 754 for Binary Floating-
Point Arithmetic and are the same exceptions that are generated for x87 FPU instruc-
tions. See Section 11.5.1, “SIMD Floating-Point Exceptions,” for a description of
these exceptions.
1. The FISTTP instruction in SSE3 does not generate SIMD floating-point exceptions, but it can gen-
erate x87 FPU floating-point exceptions.