Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 11-19
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
11.5.1 SIMD Floating-Point Exceptions
SIMD floating-point exceptions are those exceptions that can be generated by
SSE/SSE2/SSE3 instructions that operate on packed or scalar floating-point oper-
ands.
Six classes of SIMD floating-point exceptions can be generated:
• Invalid operation (#I)
• Divide-by-zero (#Z)
• Denormal operand (#D)
• Numeric overflow (#O)
• Numeric underflow (#U)
• Inexact result (Precision) (#P)
All of these exceptions (except the denormal operand exception) are defined in IEEE
Standard 754, and they are the same exceptions that are generated with the x87
floating-point instructions. Section 4.9, “Overview of Floating-Point Exceptions,”
gives a detailed description of these exceptions and of how and when they are gener-
ated. The following sections discuss the implementation of these exceptions in
SSE/SSE2/SSE3 extensions.
All SIMD floating-point exceptions are precise and occur as soon as the instruction
completes execution.
Each of the six exception conditions has a corresponding flag (IE, DE, ZE, OE, UE,
and PE) and mask bit (IM, DM, ZM, OM, UM, and PM) in the MXCSR register (see
Figure 10-3). The mask bits can be set with the LDMXCSR or FXRSTOR instruction;
the mask and flag bits can be read with the STMXCSR or FXSAVE instruction.
The OSXMMEXCEPT flag (bit 10) of control register CR4 provides additional control
over generation of SIMD floating-point exceptions by allowing the operating system
to indicate whether or not it supports software exception handlers for SIMD floating-
point exceptions. If an unmasked SIMD floating-point exception is generated and the
OSXMMEXCEPT flag is set, the processor invokes a software exception handler by
generating a SIMD floating-point exception (#XF). If the OSXMMEXCEPT bit is clear,
the processor generates an invalid-opcode exception (#UD) on the first SSE or SSE2
instruction that detects a SIMD floating-point exception condition. See Section
11.6.2, “Checking for SSE/SSE2 Support.”
11.5.2 SIMD Floating-Point Exception Conditions
The following sections describe the conditions that cause a SIMD floating-point
exception to be generated and the masked response of the processor when these
conditions are detected.
See Section 4.9.2, “Floating-Point Exception Priority,” for a description of the rules for
exception precedence when more than one floating-point exception condition is
detected for an instruction.