Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 11-21
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
If the invalid operation exception is not masked, a software exception handler is
invoked and the operands remain unchanged. See Section 11.5.4, “Handling SIMD
Floating-Point Exceptions in Software.”
Normally, when one or more of the source operands are QNaNs (and neither is an
SNaN or in an unsupported format), an invalid-operation exception is not generated.
The following instructions are exceptions to this rule: the COMISS and COMISD
instructions; and the CMPPS, CMPSS, CMPPD, and CMPSD instructions (when the
predicate is less than, less-than or equal, not less-than, or not less-than or equal).
With these instructions, a QNaN source operand will generate an invalid-operation
exception.
The invalid-operation exception is not affected by the flush-to-zero mode or by the
denormals-are-zeros mode.
11.5.2.2 Denormal-Operand Exception (#D)
The processor signals the denormal-operand exception if an arithmetic instruction
attempts to operate on a denormal operand. The flag (DE) and mask (DM) bits for
the denormal-operand exception are bits 1 and 8, respectively, in the MXCSR
register.
The CVTPI2PD, CVTPD2PI, CVTTPD2PI, CVTDQ2PD, CVTPD2DQ, CVTTPD2DQ,
CVTSI2SD, CVTSD2SI, CVTTSD2SI, CVTPI2PS, CVTPS2PI, CVTTPS2PI, CVTSS2SI,
CVTTSS2SI, CVTSI2SS, CVTDQ2PS, CVTPS2DQ, and CVTTPS2DQ conversion instruc-
tions do not signal denormal exceptions. The RCPSS, RCPPS, RSQRTSS, and
RSQRTPS instructions do not signal any kind of floating-point exception.
The denormals-are-zero flag (bit 6) of the MXCSR register provides an additional
option for handling denormal-operand exceptions. When this flag is set, denormal
source operands are automatically converted to zeros with the sign of the source
operand (see Section 10.2.3.4, “Denormals-Are-Zeros”). The denormal operand
exception is not affected by the flush-to-zero mode.
See Section 4.9.1.2, “Denormal Operand Exception (#D),” for more information
about the denormal exception. See Section 11.5.4, “Handling SIMD Floating-Point
Exceptions in Software,” for information on handling unmasked exceptions.
Conversion to integer when the value in the
source register is a NaN,
∞, or exceeds the
representable range for CVTPS2PI, CVTTPS2PI,
CVTSS2SI, CVTTSS2SI, CVTPD2PI, CVTSD2SI,
CVTPD2DQ, CVTTPD2PI, CVTTSD2SI,
CVTTPD2DQ, CVTPS2DQ, or CVTTPS2DQ
Return the integer Indefinite
Table 11-1. Masked Responses of SSE/SSE2/SSE3 Instructions to Invalid Arithmetic
Operations (Contd.)
Condition Masked Response