Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

2-2 Vol. 1
INTEL
®
64 AND IA-32 ARCHITECTURES
• Read-only and execute-only segment options
• Four privilege levels
2.1.3 The Intel386
™
Processor (1985)
The Intel386 processor was the first 32-bit processor in the IA-32 architecture family.
It introduced 32-bit registers for use both to hold operands and for addressing. The
lower half of each 32-bit Intel386 register retains the properties of the 16-bit regis-
ters of earlier generations, permitting backward compatibility. The processor also
provides a virtual-8086 mode that allows for even greater efficiency when executing
programs created for 8086/8088 processors.
In addition, the Intel386 processor has support for:
• A 32-bit address bus that supports up to 4-GBytes of physical memory
• A segmented-memory model and a flat memory model
• Paging, with a fixed 4-KByte page size providing a method for virtual memory
management
• Support for parallel stages
2.1.4 The Intel486
™
Processor (1989)
The Intel486
™
processor added more parallel execution capability by expanding the
Intel386 processor’s instruction decode and execution units into five pipelined
stages. Each stage operates in parallel with the others on up to five instructions in
different stages of execution.
In addition, the processor added:
• An 8-KByte on-chip first-level cache that increased the percent of instructions
that could execute at the scalar rate of one per clock
• An integrated x87 FPU
• Power saving and system management capabilities
2.1.5 The Intel
®
Pentium
®
Processor (1993)
The introduction of the Intel Pentium processor added a second execution pipeline to
achieve superscalar performance (two pipelines, known as u and v, together can
execute two instructions per clock). The on-chip first-level cache doubled, with 8
KBytes devoted to code and another 8 KBytes devoted to data. The data cache uses
the MESI protocol to support more efficient write-back cache in addition to the write-
through cache previously used by the Intel486 processor. Branch prediction with an
on-chip branch table was added to increase performance in looping constructs.