Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

11-22 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
11.5.2.3 Divide-By-Zero Exception (#Z)
The processor reports a divide-by-zero exception when a DIVPS, DIVSS, DIVPD or
DIVSD instruction attempts to divide a finite non-zero operand by 0. The flag (ZE)
and mask (ZM) bits for the divide-by-zero exception are bits 2 and 9, respectively, in
the MXCSR register.
See Section 4.9.1.3, “Divide-By-Zero Exception (#Z),” for more information about
the divide-by-zero exception. See Section 11.5.4, “Handling SIMD Floating-Point
Exceptions in Software,” for information on handling unmasked exceptions.
The divide-by-zero exception is not affected by the flush-to-zero mode or by the
denormals-are-zeros mode.
11.5.2.4 Numeric Overflow Exception (#O)
The processor reports a numeric overflow exception whenever the rounded result of
an arithmetic instruction exceeds the largest allowable finite value that fits in the
destination operand. This exception can be generated with the ADDPS, ADDSS,
ADDPD, ADDSD, SUBPS, SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD,
DIVPS, DIVSS, DIVPD, DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS,
HADDPD, HADDPS, HSUBPD and HSUBPS instructions. The flag (OE) and mask (OM)
bits for the numeric overflow exception are bits 3 and 10, respectively, in the MXCSR
register.
See Section 4.9.1.4, “Numeric Overflow Exception (#O),” for more information about
the numeric-overflow exception. See Section 11.5.4, “Handling SIMD Floating-Point
Exceptions in Software,” for information on handling unmasked exceptions.
The numeric overflow exception is not affected by the flush-to-zero mode or by the
denormals-are-zeros mode.
11.5.2.5 Numeric Underflow Exception (#U)
The processor reports a numeric underflow exception whenever the rounded result of
an arithmetic instruction is less than the smallest possible normalized, finite value
that will fit in the destination operand and the numeric-underflow exception is not
masked. If the numeric underflow exception is masked, both underflow and the
inexact-result condition must be detected before numeric underflow is reported. This
exception can be generated with the ADDPS, ADDSS, ADDPD, ADDSD, SUBPS,
SUBSS, SUBPD, SUBSD, MULPS, MULSS, MULPD, MULSD, DIVPS, DIVSS, DIVPD,
DIVSD, CVTPD2PS, CVTSD2SS, ADDSUBPD, ADDSUBPS, HADDPD, HADDPS,
HSUBPD, and HSUBPS instructions. The flag (UE) and mask (UM) bits for the numeric
underflow exception are bits 4 and 11, respectively, in the MXCSR register.
The flush-to-zero flag (bit 15) of the MXCSR register provides an additional option for
handling numeric underflow exceptions. When this flag is set and the numeric under-
flow exception is masked, tiny results (results that trigger the underflow exception)
are returned as a zero with the sign of the true result (see Section 10.2.3.3, “Flush-