Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 11-23
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
To-Zero”). The numeric underflow exception is not affected by the denormals-are-
zero mode.
See Section 4.9.1.5, “Numeric Underflow Exception (#U),” for more information
about the numeric underflow exception. See Section 11.5.4, “Handling SIMD
Floating-Point Exceptions in Software,” for information on handling unmasked
exceptions.
11.5.2.6 Inexact-Result (Precision) Exception (#P)
The inexact-result exception (also called the precision exception) occurs if the result
of an operation is not exactly representable in the destination format. For example,
the fraction 1/3 cannot be precisely represented in binary form. This exception
occurs frequently and indicates that some (normally acceptable) accuracy has been
lost. The exception is supported for applications that need to perform exact arith-
metic only. Because the rounded result is generally satisfactory for most applica-
tions, this exception is commonly masked.
The flag (PE) and mask (PM) bits for the inexact-result exception are bits 2 and 12,
respectively, in the MXCSR register.
See Section 4.9.1.6, “Inexact-Result (Precision) Exception (#P),” for more informa-
tion about the inexact-result exception. See Section 11.5.4, “Handling SIMD
Floating-Point Exceptions in Software,” for information on handling unmasked excep-
tions.
In flush-to-zero mode, the inexact result exception is reported. The inexact result
exception is not affected by the denormals-are-zero mode.
11.5.3 Generating SIMD Floating-Point Exceptions
When the processor executes a packed or scalar floating-point instruction, it looks for
and reports on SIMD floating-point exception conditions using two sequential steps:
1. Looks for, reports on, and handles pre-computation exception conditions
(invalid-operand, divide-by-zero, and denormal operand)
2. Looks for, reports on, and handles post-computation exception conditions
(numeric overflow, numeric underflow, and inexact result)
If both pre- and post-computational exceptions are unmasked, it is possible for the
processor to generate a SIMD floating-point exception (#XF) twice during the execu-
tion of an SSE, SSE2 or SSE3 instruction: once when it detects and handles a pre-
computational exception and when it detects a post-computational exception.
11.5.3.1 Handling Masked Exceptions
If all exceptions are masked, the processor handles the exceptions it detects by
placing the masked result (or results for packed operands) in a destination operand