Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 11-29
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
early steppings. To check for the presence of the DAZ flag in the MXCSR register, do
the following:
1. Establish a 512-byte FXSAVE area in memory.
2. Clear the FXSAVE area to all 0s.
3. Execute the FXSAVE instruction, using the address of the first byte of the cleared
FXSAVE area as a source operand. See “FXSAVE—Save x87 FPU, MMX, SSE, and
SSE2 State” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software
Developer’s Manual, Volume 2A, for a description of the FXSAVE instruction and
the layout of the FXSAVE image.
4. Check the value in the MXCSR_MASK field in the FXSAVE image (bytes 28
through 31).
— If the value of the MXCSR_MASK field is 00000000H, the DAZ flag and
denormals-are-zero mode are not supported.
— If the value of the MXCSR_MASK field is non-zero and bit 6 is set, the DAZ
flag and denormals-are-zero mode are supported.
If the DAZ flag is not supported, then it is a reserved bit and attempting to write a 1
to it will cause a general-protection exception (#GP). See Section 11.6.6, “Guidelines
for Writing to the MXCSR Register,” for general guidelines for preventing general-
protection exceptions when writing to the MXCSR register.
11.6.4 Initialization of SSE/SE2 Extensions
The SSE and SSE2 state is contained in the XMM and MXCSR registers. Upon a hard-
ware reset of the processor, this state is initialized as follows (see Table 11-2):
• All SIMD floating-point exceptions are masked (bits 7 through 12 of the MXCSR
register is set to 1).
• All SIMD floating-point exception flags are cleared (bits 0 through 5 of the MXCSR
register is set to 0).
• The rounding control is set to round-nearest (bits 13 and 14 of the MXCSR
register are set to 00B).
• The flush-to-zero mode is disabled (bit 15 of the MXCSR register is set to 0).
• The denormals-are-zeros mode is disabled (bit 6 of the MXCSR register is set to
0). If the denormals-are-zeros mode is not supported, this bit is reserved and will
be set to 0 on initialization.
• Each of the XMM registers is cleared (set to all zeros).