Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

11-30 Vol. 1
PROGRAMMING WITH STREAMING SIMD EXTENSIONS 2 (SSE2)
If the processor is reset by asserting the INIT# pin, the SSE and SSE2 state is not
changed.
11.6.5 Saving and Restoring the SSE/SSE2 State
The FXSAVE instruction saves the x87 FPU, MMX, SSE and SSE2 states (which
includes the contents of eight XMM registers and the MXCSR registers) in a 512-byte
block of memory. The FXRSTOR instruction restores the saved SSE and SSE2 state
from memory. See the FXSAVE instruction in Chapter 3 of the Intel® 64 and IA-32
Architectures Software Developer’s Manual, Volume 2A, for the layout of the
512-byte state block.
In addition to saving and restoring the SSE and SSE2 state, FXSAVE and FXRSTOR
also save and restore the x87 FPU state (because MMX registers are aliased to the
x87 FPU data registers this includes saving and restoring the MMX state). For greater
code efficiency, it is suggested that FXSAVE and FXRSTOR be substituted for the
FSAVE, FNSAVE and FRSTOR instructions in the following situations:
• When a context switch is being made in a multitasking environment
• During calls and returns from interrupt and exception handlers
In situations where the code is switching between x87 FPU and MMX technology
computations (without a context switch or a call to an interrupt or exception), the
FSAVE/FNSAVE and FRSTOR instructions are more efficient than the FXSAVE and
FXRSTOR instructions.
11.6.6 Guidelines for Writing to the MXCSR Register
The MXCSR has several reserved bits, and attempting to write a 1 to any of these bits
will cause a general-protection exception (#GP) to be generated. To allow software to
identify these reserved bits, the MXCSR_MASK value is provided. Software can deter-
mine this mask value as follows:
1. Establish a 512-byte FXSAVE area in memory.
2. Clear the FXSAVE area to all 0s.
3. Execute the FXSAVE instruction, using the address of the first byte of the cleared
FXSAVE area as a source operand. See “FXSAVE—Save x87 FPU, MMX, SSE, and
SSE2 State” in Chapter 3 of the Intel® 64 and IA-32 Architectures Software
Table 11-2. SSE and SSE2 State Following a Power-up/Reset or INIT
Registers Power-Up or
Reset
INIT
XMM0 through XMM7 +0.0 Unchanged
MXCSR 1F80H Unchanged