Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 2-3
INTEL
®
64 AND IA-32 ARCHITECTURES
In addition, the processor added:
• Extensions to make the virtual-8086 mode more efficient and allow for 4-MByte
as well as 4-KByte pages
• Internal data paths of 128 and 256 bits add speed to internal data transfers
• Burstable external data bus was increased to 64 bits
• An APIC to support systems with multiple processors
• A dual processor mode to support glueless two processor systems
A subsequent stepping of the Pentium family introduced Intel MMX technology (the
Pentium Processor with MMX technology). Intel MMX technology uses the single-
instruction, multiple-data (SIMD) execution model to perform parallel computations
on packed integer data contained in 64-bit registers.
See Section 2.2.4, “SIMD Instructions.”
2.1.6 The P6 Family of Processors (1995-1999)
The P6 family of processors was based on a superscalar microarchitecture that set
new performance standards; see also Section 2.2.1, “P6 Family Microarchitecture.”
One of the goals in the design of the P6 family microarchitecture was to exceed the
performance of the Pentium processor significantly while using the same 0.6-
micrometer, four-layer, metal BICMOS manufacturing process. Members of this
family include the following:
• The Intel Pentium Pro processor is three-way superscalar. Using parallel
processing techniques, the processor is able on average to decode, dispatch, and
complete execution of (retire) three instructions per clock cycle. The Pentium Pro
introduced the dynamic execution (micro-data flow analysis, out-of-order
execution, superior branch prediction, and speculative execution) in a
superscalar implementation. The processor was further enhanced by its caches.
It has the same two on-chip 8-KByte 1st-Level caches as the Pentium processor
and an additional 256-KByte Level 2 cache in the same package as the processor.
• The Intel Pentium II processor added Intel MMX technology to the P6 family
processors along with new packaging and several hardware enhancements. The
processor core is packaged in the single edge contact cartridge (SECC). The Level
l data and instruction caches were enlarged to 16 KBytes each, and Level 2 cache
sizes of 256 KBytes, 512 KBytes, and 1 MByte are supported. A half-clock speed
backside bus connects the Level 2 cache to the processor. Multiple low-power
states such as AutoHALT, Stop-Grant, Sleep, and Deep Sleep are supported to
conserve power when idling.
• The Pentium II Xeon processor combined the premium characteristics of
previous generations of Intel processors. This includes: 4-way, 8-way (and up)
scalability and a 2 MByte 2nd-Level cache running on a full-clock speed backside
bus.