Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 12-13
PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3
12.6.6 Packed Sign
There are six packed-sign instructions (represented by three mnemonics). Three
operate on 128-bit operands and three operate on 64-bit operands. The widths of
each data element for these instructions are 8 bit, 16 bit or 32 bit signed integers.
• PSIGNB/W/D negates each signed integer element of the destination operand if
the sign of the corresponding data element in the source operand is less than
zero.
12.6.7 Packed Align Right
There are two packed-align-right instructions (represented by one mnemonic). One
operates on 128-bit operands and the other operates on 64-bit operands. These
instructions concatenate the destination and source operand into a composite, and
extract the result from the composite according to an immediate constant.
• PALIGNR’s source operand is appended after the destination operand forming an
intermediate value of twice the width of an operand. The result is extracted from
the intermediate value into the destination operand by selecting the 128-bit or
64-bit value that are right-aligned to the byte offset specified by the immediate
value.
12.7 WRITING APPLICATIONS WITH SSSE3 EXTENSIONS
The following sections give guidelines for writing application programs and oper-
ating-system code that use SSSE3 instructions.
12.7.1 Guidelines for Using SSSE3 Extensions
The following guidelines describe how to maximize the benefits of using SSSE3
extensions:
• Ensure that the processor supports SSSE3 extensions.
• Ensure that your operating system supports SSE/SSE2/SSE3/SSSE3 extensions.
(Operating system support for the SSE extensions implies support for SSE2, the
x87, SIMD instructions of SSE3, and SSSE3.)
• Employ the optimization and scheduling techniques described in the Intel® 64
and IA-32 Architectures Optimization Reference Manual (see Section 1.4,
“Related Literature”).