Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

12-14 Vol. 1
PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3
12.7.2 Checking for SSSE3 Support
Before an application attempts to use the SIMD subset of SSSE3 extensions, the
application should follow the steps illustrated in Section 11.6.2, “Checking for
SSE/SSE2 Support.” Next, use the additional step provided below:
• Check that the processor supports the SIMD and x87 SSSE3 extensions (if
CPUID.01H:ECX.SSSE3[bit 9] = 1). See Example 12-3 for a code example.
Example 12-3. Verifying SSSE3 Support
boolean SSSE3_SIMD_works = TRUE;
try {
Issue_SSSE3_SIMD_Instructions();
// Use PHADDD
}
except (UNWIND)
{
// if we get here, SSSE3 not available
SSSE3_SIMD_works = FALSE;
}
12.8 SSE3/SSSE3 EXCEPTIONS
SSE3/SSSE3 instructions can generate the same type of memory-access and non-
numeric exceptions as other Intel 64 or IA-32 instructions. Existing exception
handlers generally handle these exceptions without code modification.
FISTTP can generate floating-point exceptions. Some SSE3 instructions can also
generate SIMD floating-point exceptions.
SSE3 additions and changes are noted in the following sections. See also: Section
11.5, “SSE, SSE2, and SSE3 Exceptions”
12.8.1 Device Not Available (DNA) Exceptions
SSE3/SSSE3 will cause a DNA Exception (#NM) if the processor attempts to execute
an SSE3 instruction while CR0.TS[bit 3] = 1. If CPUID.01H:ECX.SSE3[bit 0] = 0,
execution of an SSE3 extension will cause an invalid opcode fault regardless of the
state of CR0.TS[bit 3].