Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 12-15
PROGRAMMING WITH SSE3 AND SUPPLEMENTAL SSE3
12.8.2 Numeric Error flag and IGNNE#
Most SSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and
the IGNNE# pin. With one exception, all use the vector 19 software exception for
error reporting. The exception is FISTTP; it behaves like other x87-FP instructions.
SSSE3 instructions ignore CR0.NE[bit 5] (treats it as if it were always set) and the
IGNNE# pin. SSSE3 instructions do not cause floating-point errors.
12.8.3 Emulation
Used to emulate x87 floating-point instructions, CR0.EM[bit 2] cannot be used for
emulation of SSE3/SSSE3. If an SSE3/SSSE3 instruction executes with CR0.EM[bit
2] set, an invalid opcode exception (INT 6) is generated instead of a device not avail-
able exception (INT 7).