Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

13-2 Vol. 1
INPUT/OUTPUT
I/O address space is selected, it is the responsibility of the hardware to decode the
memory-I/O bus transaction to select I/O ports rather than memory. Data is trans-
mitted between the processor and an I/O device through the data lines.
13.3 I/O ADDRESS SPACE
The processor’s I/O address space is separate and distinct from the physical-memory
address space. The I/O address space consists of 2
16
(64K) individually addressable
8-bit I/O ports, numbered 0 through FFFFH. I/O port addresses 0F8H through 0FFH
are reserved. Do not assign I/O ports to these addresses. The result of an attempt to
address beyond the I/O address space limit of FFFFH is implementation-specific; see
the Developer’s Manuals for specific processors for more details.
Any two consecutive 8-bit ports can be treated as a 16-bit port, and any four consec-
utive ports can be a 32-bit port. In this manner, the processor can transfer 8, 16, or
32 bits to or from a device in the I/O address space. Like words in memory, 16-bit
ports should be aligned to even addresses (0, 2, 4, ...) so that all 16 bits can be
transferred in a single bus cycle. Likewise, 32-bit ports should be aligned to
addresses that are multiples of four (0, 4, 8, ...). The processor supports data trans-
fers to unaligned ports, but there is a performance penalty because one or more
extra bus cycle must be used.
The exact order of bus cycles used to access unaligned ports is undefined and is not
guaranteed to remain the same in future IA-32 processors. If hardware or software
requires that I/O ports be written to in a particular order, that order must be specified
explicitly. For example, to load a word-length I/O port at address 2H and then
another word port at 4H, two word-length writes must be used, rather than a single
doubleword write at 2H.
Note that the processor does not mask parity errors for bus cycles to the I/O address
space. Accessing I/O ports through the I/O address space is thus a possible source of
parity errors.
13.3.1 Memory-Mapped I/O
I/O devices that respond like memory components can be accessed through the
processor’s physical-memory address space (see Figure 13-1). When using memory-
mapped I/O, any of the processor’s instructions that reference memory can be used
to access an I/O port located at a physical-memory address. For example, the MOV
instruction can transfer data between any register and a memory-mapped I/O port.
The AND, OR, and TEST instructions may be used to manipulate bits in the control
and status registers of a memory-mapped peripheral devices.
When using memory-mapped I/O, caching of the address space mapped for I/O
operations must be prevented. With the Pentium 4, Intel Xeon, and P6 family proces-
sors, caching of I/O accesses can be prevented by using memory type range regis-
ters (MTRRs) to map the address space used for the memory-mapped I/O as