Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 13-3

INPUT/OUTPUT

uncacheable (UC). See Chapter 10, “Memory Cache Control,” in the Intel® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3A, for a complete discus-

sion of the MTRRs.

The Pentium and Intel486 processors do not support MTRRs. Instead, they provide

the KEN# pin, which when held inactive (high) prevents caching of all addresses sent

out on the system bus. To use this pin, external address decoding logic is required to

block caching in specific address spaces.

All the IA-32 processors that have on-chip caches also provide the PCD (page-level

cache disable) flag in page table and page directory entries. This flag allows caching

to be disabled on a page-by-page basis. See “Page-Directory and Page-Table Entries”

in Chapter 3 of in the Intel® 64 and IA-32 Architectures Software Developer’s

Manual, Volume 3A.

13.4 I/O INSTRUCTIONS

The processor’s I/O instructions provide access to I/O ports through the I/O address

space. (These instructions cannot be used to access memory-mapped I/O ports.)

There are two groups of I/O instructions:

• Those that transfer a single item (byte, word, or doubleword) between an I/O

port and a general-purpose register

Figure 13-1. Memory-Mapped I/O

FFFF FFFFH

I/O Port

EPROM

RAM

Physical Memory

I/O Port