Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

14-2 Vol. 1
PROCESSOR IDENTIFICATION AND FEATURE DETERMINATION
• Test feature identification flags individually and do not make assumptions about
undefined bits.
14.1.2 Identification of Earlier IA-32 Processors
The CPUID instruction is not available in earlier IA-32 processors up through the
earlier Intel486 processors. For these processors, several other architectural
features can be exploited to identify the processor.
The settings of bits 12 and 13 (IOPL), 14 (NT), and 15 (reserved) in the EFLAGS
register are different for Intel’s 32-bit processors than for the Intel 8086 and Intel
286 processors. By examining the settings of these bits (with the PUSHF/PUSHFD
and POP/POPFD instructions), an application program can determine whether the
processor is an 8086, Intel 286, or one of the Intel 32-bit processors:
• 8086 processor — Bits 12 through 15 of the EFLAGS register are always set.
• Intel 286 processor — Bits 12 through 15 are always clear in real-address mode.
• 32-bit processors — In real-address mode, bit 15 is always clear and bits 12
through 14 have the last value loaded into them. In protected mode, bit 15 is
always clear, bit 14 has the last value loaded into it, and the IOPL bits depends on
the current privilege level (CPL). The IOPL field can be changed only if the CPL is 0.
Other EFLAG register bits that can be used to differentiate between the 32-bit
processors:
• Bit 18 (AC) — Implemented only on the Pentium 4, Intel Xeon, P6 family,
Pentium, and Intel486 processors. The inability to set or clear this bit distin-
guishes an Intel386 processor from the later IA-32 processors.
• Bit 21 (ID) — Determines if the processor is able to execute the CPUID
instruction. The ability to set and clear this bit indicates that it is a Pentium 4,
Intel Xeon, P6 family, Pentium, or later-version Intel486 processor.
To determine whether an x87 FPU or NPX is present in a system, applications can
write to the x87 FPU status and control registers using the FNINIT instruction and
then verify that the correct values are read back using the FNSTENV instruction.
After determining that an x87 FPU or NPX is present, its type can then be deter-
mined. In most cases, the processor type will determine the type of FPU or NPX;
however, an Intel386 processor is compatible with either an Intel 287 or Intel 387
math coprocessor.
The method the coprocessor uses to represent ∞ (after the execution of the FINIT,
FNINIT, or RESET instruction) indicates which coprocessor is present. The Intel 287
math coprocessor uses the same bit representation for +∞ and −∞; whereas, the
Intel 387 math coprocessor uses different representations for +∞ and −∞.