Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 2-7
INTEL
®
64 AND IA-32 ARCHITECTURES
2.2.1 P6 Family Microarchitecture
The Pentium Pro processor introduced a new microarchitecture commonly referred to
as P6 processor microarchitecture. The P6 processor microarchitecture was later
enhanced with an on-die, Level 2 cache, called Advanced Transfer Cache.
The microarchitecture is a three-way superscalar, pipelined architecture. Three-way
superscalar means that by using parallel processing techniques, the processor is able
on average to decode, dispatch, and complete execution of (retire) three instructions
per clock cycle. To handle this level of instruction throughput, the P6 processor family
uses a decoupled, 12-stage superpipeline that supports out-of-order instruction
execution.
Figure 2-1 shows a conceptual view of the P6 processor microarchitecture pipeline
with the Advanced Transfer Cache enhancement.
To ensure a steady supply of instructions and data for the instruction execution pipe-
line, the P6 processor microarchitecture incorporates two cache levels. The Level 1
cache provides an 8-KByte instruction cache and an 8-KByte data cache, both closely
Figure 2-1. The P6 Processor Microarchitecture with Advanced Transfer Cache
Enhancement
Bus Unit
2nd Level Cache
On-die, 8-way
1st Level Cache
4-way, low latency
Fetch/
Decode
Execution
Instruction
Cache
Microcode
ROM
Execution
Out-of-Order
Core
Retirement
BTSs/Branch Prediction
System Bus
Branch History Update
Frequently used
Less frequently used
Front End
OM16520