Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 C-1
APPENDIX C
FLOATING-POINT EXCEPTIONS SUMMARY
C.1 OVERVIEW
This appendix shows which of the floating-point exceptions can be generated for:
• x87 FPU instructions — see Table C-2
• SSE instructions — see Table C-3
• SSE2 instructions — see Table C-4
• SSE3 instructions — see Table C-5
Table C-1 lists types of floating-point exceptions that potentially can be generated by
the x87 FPU and by SSE/SSE2/SSE3 instructions.
The floating point exceptions shown in Table C-1 (except for #D and #IS) are defined
in IEEE Standard 754-1985 for Binary Floating-Point Arithmetic. See Section 4.9.1,
“Floating-Point Exception Conditions,” for a detailed discussion of floating-point
exceptions.
Table C-1. x87 FPU and SIMD Floating-Point Exceptions
Floating-
point
Exception Description
#IS Invalid-operation exception for stack underflow or stack overflow (can only be
generated for x87 FPU instructions)*
#IA or #I Invalid-operation exception for invalid arithmetic operands and unsupported
formats*
#D Denormal-operand exception
#Z Divide-by-zero exception
#
O Numeric-overflow exception
#U Numeric-underflow exception
#P Inexact-result (precision) exception
NOTE:
* The x87 FPU instruction set generates two types of invalid-operation exceptions: #IS (stack
underflow or stack overflow) and #IA (invalid arithmetic operation due to invalid arithmetic
operands or unsupported formats). SSE/SSE2/SSE3 instructions potentially generate #I (invalid
operation exceptions due to invalid arithmetic operands or unsupported formats).