Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

C-4 Vol. 1

FLOATING-POINT EXCEPTIONS SUMMARY

C.3 SSE INSTRUCTIONS

Table C-3 lists SSE instructions with at least one of the following characteristics:

• have floating-point operands

• generate floating-point results

• read or write floating-point status and control information

The table also summarizes the floating-point exceptions that each instruction can

generate.

FUCOM(P)(P) Unordered compare floating-

point

YYY

FWAIT CPU Wait

FXAM Examine

FXCH Exchange registers Y

FXTRACT Extract YYYY

FYL2X Logarithm YYYYYYY

FYL2XP1 Logarithm epsilon Y Y Y Y Y Y

Table C-3. Exceptions Generated with SSE Instructions

Mnemonic Instruction #I #D #Z #O #U #P

ADDPS Packed add. YY YYY

ADDSS Scalar add. YY YYY

ANDNPS Packed logical INVERT and

AND.

ANDPS Packed logical AND.

CMPPS Packed compare. Y Y

CMPSS Scalar compare. Y Y

COMISS Scalar ordered compare lower

SP FP numbers and set the

status flags.

CVTPI2PS Convert two 32-bit signed

integers from MM2/Mem to

two SP FP.

Table C-2. Exceptions Generated with x87 FPU Floating-Point Instructions (Contd.)

Mnemonic Instruction #IS #IA #D #Z #O #U #P