Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 C-11
FLOATING-POINT EXCEPTIONS SUMMARY
C.5 SSE3 INSTRUCTIONS
Table C-5 lists the SSE3 instructions that have at least one of the following character-
istics:
• have floating-point operands
• generate floating-point results
For each instruction, the table summarizes the floating-point exceptions that the
instruction can generate.
SUBPD Subtract Packed Double-
Precision.
YY YYY
SUBSD Subtract Scaler Double-
Precision.
YY YYY
UCOMISD Compare lower DP FP number
in XMM1 register with lower
DP FP number in XMM2/Mem
and set the status flags
accordingly.
YY
UNPCKHPD Interleaves DP FP numbers
from the high halves of XMM1
and XMM2/Mem into XMM1
register.
UNPCKLPD Interleaves DP FP numbers
from the low halves of XMM1
and XMM2/Mem into XMM1
register.
XORPD XOR 128 bits from
XMM2/Mem to XMM1 register.
Table C-5. Exceptions Generated with SSE3 Instructions
Instruction Description #I #D #Z #O #U #P
ADDSUBPD Add /Sub packed DP FP
numbers from XMM2/Mem to
XMM1.
YY YYY
ADDSUBPS Add /Sub packed SP FP
numbers from XMM2/Mem to
XMM1.
YY YYY
Table C-4. Exceptions Generated with SSE2 Instructions (Contd.)
Instruction Description #I #D #Z #O #U #P