Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 D-3
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
as the Intel 286 and 287 processors. And again, to maintain compatibility with
existing MS-DOS software, basically the same MS-DOS compatibility floating-point
exception handling mechanism that was used in the IBM PC AT was used in PCs based
on the Intel386 processor.
D.2 IMPLEMENTATION OF THE MS-DOS COMPATIBILITY
SUB-MODE IN THE INTEL486, PENTIUM, AND P6
PROCESSOR FAMILY, AND PENTIUM 4 PROCESSORS
Beginning with the Intel486 processor, the IA-32 architecture provided a dedicated
mechanism for enabling the MS-DOS compatibility mode for x87 FPU exceptions
and for generating external x87 FPU-exception signals while operating in this mode.
The following sections describe the implementation of the MS-DOS compatibility
mode in the Intel486 and Pentium processors and in the P6 family and Pentium 4
processors. Also described is the recommended external hardware to support this
mode of operation.
D.2.1 MS-DOS Compatibility Sub-mode in the Intel486 and
Pentium Processors
In the Intel486 processor, several things were done to enhance and speed up the
numeric coprocessor, now called the floating-point unit (x87 FPU). The most impor-
tant enhancement was that the x87 FPU was included in the same chip as the
processor, for increased speed in x87 FPU computations and reduced latency for x87
FPU exception handling. Also, for the first time, the MS-DOS compatibility mode was
built into the chip design, with the addition of the NE bit in control register CR0 and
the addition of the FERR# (Floating-point ERRor) and IGNNE# (IGNore Numeric
Error) pins.
The NE bit selects the native x87 FPU exception handling mode (NE = 1) or the
MS-DOS compatibility mode (NE = 0). When native mode is selected, all signaling of
floating-point exceptions is handled internally in the Intel486 chip, resulting in the
generation of an interrupt 16.
When MS-DOS compatibility mode is selected, the FERRR# and IGNNE# pins are
used to signal floating-point exceptions. The FERR# output pin, which replaces the
ERROR# pin from the previous generations of IA-32 numeric coprocessors, is
connected to a PIC. A new input signal, IGNNE#, is provided to allow the x87 FPU
exception handler to execute x87 FPU instructions, if desired, without first clearing
the error condition and without triggering the interrupt a second time. This IGNNE#
feature is needed to replicate the capability that was provided on MS-DOS compat-
ible Intel 286 and Intel 287 and Intel386 and Intel 387 systems by turning off the
BUSY# signal, when inside the x87 FPU exception handler, before clearing the error
condition.