Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

D-4 Vol. 1
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
Note that Intel, in order to provide Intel486 processors for market segments that had
no need for an x87 FPU, created the “SX” versions. These Intel486 SX processors did
not contain the floating-point unit. Intel also produced Intel 487 SX processors for
end users who later decided to upgrade to a system with an x87 FPU. These Intel 487
SX processors are similar to standard Intel486 processors with a working x87 FPU on
board.
Thus, the external circuitry necessary to support the MS-DOS compatibility mode for
Intel 487 SX processors is the same as for standard Intel486 DX processors.
The Pentium, P6 family, and Pentium 4 processors offer the same mechanism (the NE
bit and the FERR# and IGNNE# pins) as the Intel486 processors for generating x87
FPU exceptions in MS-DOS compatibility mode. The actions of these mechanisms are
slightly different and more straightforward for the P6 family and Pentium 4 proces-
sors, as described in Section D.2.2, “MS-DOS Compatibility Sub-mode in the P6
Family and Pentium 4 Processors.”
For Pentium, P6 family, and Pentium 4 processors, it is important to note that the
special DP (Dual Processing) mode for Pentium processors and also the more general
Intel MultiProcessor Specification for systems with multiple Pentium, P6 family, or
Pentium 4 processors support x87 FPU exception handling only in the native mode.
Intel does not recommend using the MS-DOS compatibility x87 FPU mode for
systems using more than one processor.
D.2.1.1 Basic Rules: When FERR# Is Generated
When MS-DOS compatibility mode is enabled for the Intel486 or Pentium processors
(NE bit is set to 0) and the IGNNE# input pin is de-asserted, the FERR# signal is
generated as follows:
1. When an x87 FPU instruction causes an unmasked x87 FPU exception, the
processor (in most cases) uses a “deferred” method of reporting the error. This
means that the processor does not respond immediately, but rather freezes just
before executing the next WAIT or x87 FPU instruction (except for “no-wait”
instructions, which the x87 FPU executes regardless of an error condition).
2. When the processor freezes, it also asserts the FERR# output.
3. The frozen processor waits for an external interrupt, which must be supplied by
external hardware in response to the FERR# assertion.
4. In MS-DOS compatibility systems, FERR# is fed to the IRQ13 input in the
cascaded PIC. The PIC generates interrupt 75H, which then branches to interrupt
2, as described earlier in this appendix for systems using the Intel 286 and Intel
287 or Intel386 and Intel 387 processors.
The deferred method of error reporting is used for all exceptions caused by the basic
arithmetic instructions (including FADD, FSUB, FMUL, FDIV, FSQRT, FCOM and
FUCOM), for precision exceptions caused by all types of x87 FPU instructions, and for
numeric underflow and overflow exceptions caused by all types of x87 FPU instruc-
tions except stores to memory.