Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 D-9
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
which is not an explicitly documented behavior of a no-wait instruction. This process
is illustrated in Figure D-3.
Figure D-3 assumes that a floating-point instruction that generates a “deferred”
error (as defined in the Section D.2.1.1, “Basic Rules: When FERR# Is Generated”),
which asserts the FERR# pin only on encountering the next floating-point instruction,
causes an unmasked numeric exception. Assume that the next floating-point instruc-
tion following this instruction is one of the no-wait floating-point instructions. The
FERR# pin is asserted by the processor to indicate the pending exception on encoun-
tering the no-wait floating-point instruction. After the assertion of the FERR# pin the
no-wait floating-point instruction opens a window where the pending external inter-
rupts are sampled.
Then there are two cases possible depending on the timing of the receipt of the inter-
rupt via the INTR pin (asserted by the system in response to the FERR# pin) by the
processor.
Case 1 If the system responds to the assertion of FERR# pin by the no-wait
floating-point instruction via the INTR pin during this window then
the interrupt is serviced first, before resuming the execution of the
no-wait floating-point instruction.
Case 2 If the system responds via the INTR pin after the window has closed
then the interrupt is recognized only at the next instruction boundary.
Figure D-3. Timing of Receipt of External Interrupt
Assertion of FERR#
Exception Generating
Floating-Point
Instruction
by the Processor
System
Assertion of INTR Pin
by the System
Case 1
Case 2
Start of the “No-Wait”
Floating-Point
Instruction
External Interrupt
Sampling Window
Window Closed
Dependent
Delay