Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

2-10 Vol. 1
INTEL
®
64 AND IA-32 ARCHITECTURES
2.2.2.1 The Front End Pipeline
The front end supplies instructions in program order to the out-of-order execution
core. It performs a number of functions:
• Prefetches instructions that are likely to be executed
• Fetches instructions that have not already been prefetched
• Decodes instructions into micro-operations
• Generates microcode for complex instructions and special-purpose code
• Delivers decoded instructions from the execution trace cache
• Predicts branches using highly advanced algorithm
The pipeline is designed to address common problems in high-speed, pipelined
microprocessors. Two of these problems contribute to major sources of delays:
• time to decode instructions fetched from the target
Figure 2-2. The Intel NetBurst Microarchitecture
Fetch/Decode
Trace Cache
Microcode ROM
Execution
Out-Of-Order
Core
Retirement
1st Level Cache
4-way
2nd Level Cache
8-Way
BTBs/Branch Prediction
Bus Unit
System Bus
Frequently used paths
Less frequently used
paths
Front End
3rd Level Cache
Optional
Branch History Update
OM16521