Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 D-29
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
IA-32 Architectures Software Developer’s Manual, Volume 2A, for information
about exceptions generated if the memory region is not aligned).
3. Maintaining compatibility with legacy applications/libraries — The
operating system changes to support Streaming SIMD Extensions must be
invisible to legacy applications or libraries that deal only with floating-point
instructions. The layout of the memory region operated on by the
FXSAVE/FXRSTOR instructions is different from the layout for the
FNSAVE/FRSTOR instructions. Specifically, the format of the x87 FPU tag word
and the length of the various fields in the memory region is different. Care must
be taken to return the x87 FPU state to a legacy application (e.g., when reporting
FP exceptions) in the format it expects.
4. Instruction semantic differences — There are some semantic differences
between the way the FXSAVE and FSAVE/FNSAVE instructions operate. The
FSAVE/FNSAVE instructions clear the x87 FPU after they save the state while the
FXSAVE instruction saves the x87 FPU/Streaming SIMD Extensions state but
does not clear it. Operating systems that use FXSAVE to save the x87 FPU state
before making it available for another thread (e.g., during thread switch time)
should take precautions not to pass a “dirty” x87 FPU to another application.
D.4 DIFFERENCES FOR HANDLERS USING NATIVE MODE
The 8087 has an INT pin which it asserts when an unmasked exception occurs. But
there is no interrupt input pin in the 8086 or 8088 dedicated to its attachment, nor an
interrupt vector number in the 8086 or 8088 specific for an x87 FPU error assertion.
Beginning with the Intel 286 and Intel 287 hardware, a connection was dedicated to
support the x87 FPU exception and interrupt vector 16 was assigned to it.
D.4.1 Origin with the Intel 286 and Intel 287, and Intel386
and Intel 387 Processors
The Intel 286 and Intel 287, and Intel386 and Intel 387 processor/coprocessor pairs
are each provided with ERROR# pins that are recommended to be connected
between the processor and x87 FPU. If this is done, when an unmasked x87 FPU
exception occurs, the x87 FPU records the exception, and asserts its ERROR# pin.
The processor recognizes this active condition of the ERROR# status line immediately
before execution of the next WAIT or x87 FPU instruction (except for the no-wait
type) in its instruction stream, and branches to the routine at interrupt vector 16.
Thus an x87 FPU exception will be handled before any other x87 FPU instruction
(after the one causing the error) is executed (except for no-wait instructions, which
will be executed without triggering the x87 FPU exception interrupt, but it will remain
pending).