Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 D-31
GUIDELINES FOR WRITING X87 FPU EXCEPTION HANDLERS
discussed above, FERR# gets asserted independent of the value of the NE bit, but
when NE = 1, the operating system should not enable its path through the PIC.)
Another possible (very rare) way a floating-point exception interrupt could occur
while the kernel is executing is by an x87 FPU immediate exception case having its
interrupt delayed by the external hardware until execution has switched to the
kernel. This also cannot happen in native mode because there is no delay through
external hardware.
Thus the native mode x87 FPU exception handler can omit the test to see if the kernel
is the x87 FPU owner, and the DNA handler for a native mode system can omit the
step of setting the kernel as the x87 FPU owner at the handler’s beginning. Since
however these simplifications are minor and save little code, it would be a reasonable
and conservative habit (as long as the MS-DOS compatibility mode is widely used) to
include these steps in all systems.
Note that the special DP (Dual Processing) mode for Pentium processors, and also
the more general Intel MultiProcessor Specification for systems with multiple
Pentium, P6 family, or Pentium 4 processors, support x87 FPU exception handling
only in the native mode. Intel does not recommend using the MS-DOS compatibility
mode for systems using more than one processor.