Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-3
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
tion Implementation,” assume that the body of the handler (not shown here in detail)
passes the saved state to a routine that will examine in turn all the sub-operands of
the excepting instruction, invoking a user floating-point exception handler if a partic-
ular set of sub-operands raises an unmasked (enabled) exception, or emulating the
instruction otherwise.
Example 5-1. SIMD Floating-Point Exception Handler
SIMD_FP_EXC_HANDLER PROC
;PROLOGUE
;SAVE REGISTERS THAT MIGHT BE USED BY THE EXCEPTION HANDLER
PUSH EBP ;SAVE EBP
PUSH EAX ;SAVE EAX
...
MOV EBP, ESP ;SAVE ESP in EBP
SUB ESP, 512 ;ALLOCATE 512 BYTES
AND ESP, 0fffffff0h ;MAKE THE ADDRESS 16-BYTE ALIGNED
FXSAVE [ESP] ;SAVE FP, MMX, AND SIMD FP STATE
PUSH [EBP+EFLAGS_OFFSET] ;COPY OLD EFLAGS TO STACK TOP
POPFD ;RESTORE THE INTERRUPT ENABLE FLAG IF
;TO VALUE BEFORE SIMD FP EXCEPTION
;BODY
;APPLICATION-DEPENDENT EXCEPTION HANDLING CODE GOES HERE
LDMXCSR LOCAL_MXCSR ;LOAD LOCAL MXCSR VALUE IF NEEDED
...
...
;EPILOGUE
FXRSTOR [ESP] ;RESTORE MODIFIED STATE IMAGE
MOV ESP, EBP ;DE-ALLOCATE STACK SPACE
...
POP EAX ;RESTORE EAX
POP EBP ;RESTORE EBP
IRET ;RETURN TO INTERRUPTED CALCULATION
SIMD_FP_EXC_HANDLER ENDP
E.3 EXCEPTION SYNCHRONIZATION
An SSE/SSE2/SSE3 instruction can execute in parallel with other similar instructions,
with integer instructions, and with floating-point or MMX instructions. Unlike for x87
instructions, special precaution for exception synchronization is not necessary in
this case. This is because floating-point exceptions for SSE/SSE2/SSE3 instructions