Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

2-12 Vol. 1

INTEL

64 AND IA-32 ARCHITECTURES

2.2.3 Intel

Core

™

Microarchitecture

Intel Core microarchitecture introduces the following features that enable high

performance and power-efficient performance for single-threaded as well as multi-

threaded workloads:

• Intel

Wide Dynamic Execution enable each processor core to fetch,

dispatch, execute in high bandwidths to support retirement of up to four instruc-

tions per cycle.

— Fourteen-stage efficient pipeline

— Three arithmetic logical units

— Four decoders to decode up to five instruction per cycle

— Macro-fusion and micro-fusion to improve front-end throughput

— Peak issue rate of dispatching up to six micro-ops per cycle

— Peak retirement bandwidth of up to 4 micro-ops per cycle

— Advanced branch prediction

— Stack pointer tracker to improve efficiency of executing function/procedure

entries and exits

• Intel

Advanced Smart Cache delivers higher bandwidth from the second

level cache to the core, and optimal performance and flexibility for single-

threaded and multi-threaded applications.

— Large second level cache up to 4 MB and 16-way associativity

— Optimized for multicore and single-threaded execution environments

— 256 bit internal data path to improve bandwidth from L2 to first-level data

cache

• Intel

Smart Memory Access prefetches data from memory in response to

data access patterns and reduces cache-miss exposure of out-of-order

execution.

— Hardware prefetchers to reduce effective latency of second-level cache

misses

— Hardware prefetchers to reduce effective latency of first-level data cache

misses

— Memory disambiguation to improve efficiency of speculative execution

execution engine

• Intel

Advanced Digital Media Boost improves most 128-bit SIMD instruction

with single-cycle throughput and floating-point operations.

— Single-cycle throughput of most 128-bit SIMD instructions

— Up to eight floating-point operation per cycle

— Three issue ports available to dispatching SIMD instructions for execution