Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

E-6 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
A diagram of the control flow in handling an unmasked floating-point exception is
presented below.
From the user-level floating-point filter, Example E-1 in Section E.4.3, “Example
SIMD Floating-Point Emulation Implementation,” will present only the floating-point
emulation part. In order to understand the actions involved, the expected response
to exceptions has to be known for all SSE/SSE2/SSE3 numeric instructions in two
situations: with exceptions enabled (unmasked result), and with exceptions disabled
(masked result). The latter can be found in Section 6.4, “Interrupts and Exceptions.”
The response to NaN operands that do not raise an exception is specified in Section
4.8.3.4, “NaNs.” Operations on NaNs are explained in the same source. This response
is also discussed in more detail in the next subsection, along with the unmasked and
masked responses to floating-point exceptions.
E.4.2 SSE/SSE2/SSE3 Response To Floating-Point Exceptions
This subsection specifies the unmasked response expected from the SSE/SSE2/SSE3
instructions that raise floating-point exceptions. The masked response is given in
parallel, as it is necessary in the emulation process of the instructions that raise
unmasked floating-point exceptions. The response to NaN operands is also included
in more detail than in Section 4.8.3.4, “NaNs.” For floating-point exception priority,
refer to “Priority Among Simultaneous Exceptions and Interrupts” in Chapter 5,
Figure E-1. Control Flow for Handling Unmasked Floating-Point Exceptions
User Application
User Level Floating-Point Exception Filter
Low-Level Floating-Point Exception Handler
User Floating-Point Exception Handler