Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

E-8 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-1. ADDPS, ADDSS, SUBPS, SUBSS, MULPS, MULSS, DIVPS, DIVSS, ADDPD,
ADDSD, SUBPD, SUBSD, MULPD, MULSD, DIVPD, DIVSD, ADDSUBPS, ADDSUBPD,
HADDPS, HADDPD, HSUBPS, HSUBPD
Source Operands Masked Result Unmasked Result
SNaN1 op
1
SNaN2 SNaN1 | 00400000H or
SNaN1 |
0008000000000000H
2
None
SNaN1 op QNaN2 SNaN1 | 00400000H or
SNaN1 |
0008000000000000H
2
None
QNaN1 op SNaN2 QNaN1 None
QNaN1 op QNaN2 QNaN1 QNaN1 (not an exception)
SNaN op real value SNaN | 00400000H or
SNaN1 |
0008000000000000H
2
None
Real value op SNaN SNaN | 00400000H or
SNaN1 |
0008000000000000H
2
None
QNaN op real value QNaN QNaN (not an exception)
Real value op QNaN QNaN QNaN (not an exception)
Neither source operand is
SNaN,
but #I is signaled (e.g. for Inf -
Inf,
Inf ∗ 0, Inf / Inf, 0/0)
Single precision or double
precision QNaN Indefinite
None
NOTES:
1. For Tables E-1 to E-12: op denotes the operation to be performed.
2. SNaN | 0x00400000 is a quiet NaN in single precision format (if SNaN is in single precision) and
SNaN | 0008000000000000H is a quiet NaN in double precision format (if SNaN is in double
precision), obtained from the signaling NaN given as input.
3. Operations involving only quiet NaNs do not raise floating-point exceptions.