Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-9
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-2. CMPPS.EQ, CMPSS.EQ, CMPPS.ORD, CMPSS.ORD,
CMPPD.EQ, CMPSD.EQ, CMPPD.ORD, CMPSD.ORD
Source Operands Masked Result Unmasked Result
NaN op Opd2 (any Opd2) 00000000H or
0000000000000000H
1
00000000H or
0000000000000000H
1
(not
an exception)
Opd1 op NaN (any Opd1) 00000000H or
0000000000000000H
1
00000000H or
0000000000000000H
1
(not
an exception)
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-3. CMPPS.NEQ, CMPSS.NEQ, CMPPS.UNORD, CMPSS.UNORD, CMPPD.NEQ,
CMPSD.NEQ, CMPPD.UNORD, CMPSD.UNORD
Source Operands Masked Result Unmasked Result
NaN op Opd2 (any Opd2) FFFFFFFFH or
FFFFFFFFFFFFFFFFH
1
FFFFFFFFH or
FFFFFFFFFFFFFFFFH
1
(not an
exception)
Opd1 op NaN (any Opd1) FFFFFFFFH or
FFFFFFFFFFFFFFFFH
1
FFFFFFFFH or
FFFFFFFFFFFFFFFFH
1
(not an
exception)
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-4. CMPPS.LT, CMPSS.LT, CMPPS.LE, CMPSS.LE, CMPPD.LT, CMPSD.LT,
CMPPD.LE, CMPSD.LE
Source Operands Masked Result Unmasked Result
NaN op Opd2 (any Opd2) 00000000H or
0000000000000000H
1
None
Opd1 op NaN (any Opd1) 00000000H or
0000000000000000H
1
None
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.