Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

E-10 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-5. CMPPS.NLT, CMPSS.NLT, CMPPS.NLE, CMPSS.NLE, CMPPD.NLT, CMPSD.NLT,
CMPPD.NLE, CMPSD.NLE
Source Operands Masked Result Unmasked Result
NaN op Opd2 (any Opd2) FFFFFFFFH or
FFFFFFFFFFFFFFFFH
1
None
Opd1 op NaN (any Opd1) FFFFFFFFH or
FFFFFFFFFFFFFFFFH
1
None
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-6. COMISS, COMISD
Source Operands Masked Result Unmasked Result
SNaN op Opd2 (any Opd2) OF, SF, AF = 000
ZF, PF, CF = 111
None
Opd1 op SNaN (any Opd1) OF, SF, AF = 000
ZF, PF, CF = 111
None
QNaN op Opd2 (any Opd2) OF, SF, AF = 000
ZF, PF, CF = 111
None
Opd1 op QNaN (any Opd1) OF, SF, AF = 000
ZF, PF, CF = 111
None
Table E-7. UCOMISS, UCOMISD
Source Operands Masked Result Unmasked Result
SNaN op Opd2 (any Opd2) OF, SF, AF = 000
ZF, PF, CF = 111
None
Opd1 op SNaN (any Opd1) OF, SF, AF = 000
ZF, PF, CF = 111
None
QNaN op Opd2
(any Opd2
≠ SNaN)
OF, SF, AF = 000
ZF, PF, CF = 111
OF, SF, AF = 000
ZF, PF, CF = 111 (not an
exception)
Opd1 op QNaN
(any Opd1 ≠ SNaN)
OF, SF, AF = 000
ZF, PF, CF = 111
OF, SF, AF = 000
ZF, PF, CF = 111 (not an
exception)