Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-11
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
Table E-8. CVTPS2PI, CVTSS2SI, CVTTPS2PI, CVTTSS2SI, CVTPD2PI, CVTSD2SI,
CVTTPD2PI, CVTTSD2SI, CVTPS2DQ, CVTTPS2DQ, CVTPD2DQ, CVTTPD2DQ
Source Operand Masked Result Unmasked Result
SNaN 80000000H or
8000000000000000
1
(Integer Indefinite)
None
QNaN 80000000H or
8000000000000000
1
(Integer Indefinite)
None
NOTE:
1. 32-bit results are for single, and 64-bit results for double precision operations.
Table E-9. MAXPS, MAXSS, MINPS, MINSS, MAXPD, MAXSD, MINPD, MINSD
Source Operands Masked Result Unmasked Result
Opd1 op NaN2 (any Opd1) NaN2 None
NaN1 op Opd2 (any Opd2) Opd2 None
NOTE:
1. SNaN and QNaN operands raise an Invalid Operation fault.
Table E-10. SQRTPS, SQRTSS, SQRTPD, SQRTSD
Source Operand Masked Result Unmasked Result
QNaN QNaN QNaN (not an exception)
SNaN SNaN | 00400000H or
SNaN |
0008000000000000H
1
None
Source operand is not SNaN;
but #I is signaled (e.g. for
sqrt (-1.0))
Single precision or
double precision QNaN
Indefinite
None
NOTE:
1. SNaN | 00400000H is a quiet NaN in single precision format (if SNaN is in single precision) and
SNaN | 0008000000000000H is a quiet NaN in double precision format (if SNaN is in double
precision), obtained from the signaling NaN given as input.