Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

E-12 Vol. 1
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
E.4.2.3 Condition Codes, Exception Flags, and Response for Masked and
Unmasked Numeric Exceptions
In the following, the masked response is what the processor provides when a masked
exception is raised by an SSE/SSE2/SSE3 numeric instruction. The same response is
provided by the floating-point emulator for SSE/SSE2/SSE3 numeric instructions,
when certain components of the quadruple input operands generate exceptions that
are masked (the emulator also generates the correct answer, as specified by IEEE
Standard 754 wherever applicable, in the case when no floating-point exception
occurs). The unmasked response is what the emulator provides to the user handler
for those components of the packed operands of SSE/SSE2/SSE3 instructions that
raise unmasked exceptions. Note that for pre-computation exceptions (floating-point
Table E-11. CVTPS2PD, CVTSS2SD
Source Operands Masked Result Unmasked Result
QNaN QNaN1
1
QNaN1
1
(not an exception)
SNaN QNaN1
2
None
NOTES:
1. The double precision output QNaN1 is created from the single precision input QNaN as follows:
the sign bit is preserved, the 8-bit exponent FFH is replaced by the 11-bit exponent 7FFH, and
the 24-bit significand is extended to a 53-bit significand by appending 29 bits equal to 0.
2. The double precision output QNaN1 is created from the single precision input SNaN as follows:
the sign bit is preserved, the 8-bit exponent FFH is replaced by the 11-bit exponent 7FFH, and
the 24-bit significand is extended to a 53-bit significand by pending 29 bits equal to 0. The sec-
ond most significant bit of the significand is changed from 0 to 1 to convert the signaling NaN
into a quiet NaN.
Table E-12. CVTPD2PS, CVTSD2SS
Source Operands Masked Result Unmasked Result
QNaN QNaN1
1
QNaN1
1
(not an exception)
SNaN QNaN1
2
None
NOTES:
1. The single precision output QNaN1 is created from the double precision input QNaN as follows:
the sign bit is preserved, the 11-bit exponent 7FFH is replaced by the 8-bit exponent FFH, and
the 53-bit significand is truncated to a 24-bit significand by removing its 29 least significant
bits.
2. The single precision output QNaN1 is created from the double precision input SNaN as follows:
the sign bit is preserved, the 11-bit exponent 7FFH is replaced by the 8-bit exponent FFH, and
the 53-bit significand is truncated to a 24-bit significand by removing its 29 least significant
bits. The second most significant bit of the significand is changed from 0 to 1 to convert the sig-
naling NaN into a quiet NaN.