Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 E-13
GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS
faults), no result is provided to the user handler. For post-computation exceptions
(floating-point traps), a result is provided to the user handler, as specified below.
In the following tables, the result is denoted by 'res', with the understanding that for
the actual instruction, the destination coincides with the first source operand (except
for COMISS, UCOMISS, COMISD, and UCOMISD, whose destination is the EFLAGS
register).
Table E-13. #I - Invalid Operations
Instruction Condition Masked Response
Unmasked
Response and
Exception Code
ADDPS
ADDPD
ADDSS
ADDSD
HADDPS
HADDPD
src1 or src2
1
= SNaN Refer to Table E-1 for
NaN operands, #IA = 1
src1, src2
unchanged; #IA =
1
ADDSUBPS (the
addition
component)
ADDSUBPD (the
addition
component)
src1 = +Inf, src2 = -Inf or
src1 = -Inf, src2 = +Inf
res
1
= QNaN Indefinite,
#IA = 1
SUBPS
SUBPD
SUBSS
SUBSD
HSUBPS
HSUBPD
src1 or src2 = SNaN Refer to Table E-1 for NaN
operands, #IA = 1
src1, src2
unchanged; #IA =
1
ADDSUBPS (the
subtraction
component)
ADDSUBPD (the
subtraction
component)
src1 = +Inf, src2 = +Inf or
src1 = -Inf, src2 = -Inf
res = QNaN Indefinite,
#IA = 1
MULPS
MULPD
src1 or src2 = SNaN Refer to Table E-1 for
NaN operands, #IA = 1
src1, src2
unchanged;
#IA = 1
MULSS
MULSD
src1 = ±Inf, src2 = ±0 or
src1 = ±0, src2 = ±Inf
res = QNaN Indefinite,
#IA = 1
DIVPS
DIVPD
src1 or src2 = SNaN Refer to Table E-1 for
NaN operands, #IA = 1
src1, src2
unchanged;
#IA = 1
DIVSS
DIVSD
src1 = ±Inf, src2 = ±Inf or
src1 = ±0, src2 = ±0
res = QNaN Indefinite,
#IA = 1