Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

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Vol. 1 E-15

GUIDELINES FOR WRITING SIMD FLOATING-POINT EXCEPTION HANDLERS

CVTPS2PI

CVTSS2SI

CVTPD2PI

CVTSD2SI

CVTPS2DQ

CVTPD2DQ

src = NaN, ±Inf, or

|(src)

rnd

| > 7FFFFFFFH and

(src)

rnd

≠ 80000000H

See Note

for information

on rnd.

res = Integer Indefinite,

#IA = 1

src unchanged,

#IA = 1

CVTTPS2PI

CVTTSS2SI

CVTTPD2PI

CVTTSD2SI

CVTTPS2DQ

CVTTPD2DQ

src = NaN, ±Inf, or

|(src)

| > 7FFFFFFFH

and

(src)

≠ 80000000H

See Note

for information

on rz.

res = Integer Indefinite,

#IA = 1

src unchanged,

#IA = 1

CVTPS2PD

CVTSS2SD

src = NAN Refer to Table E-11 for

NaN operands

src unchanged,

#IA = 1

CVTPD2PS

CVTSD2SS

src = NAN Refer to Table E-12 for

NaN operands

src unchanged,

#IA = 1

NOTES:

1. For Tables E-13 to E-18:

- src denotes the single source operand of a unary operation.

- src1, src2 denote the first and second source operand of a binary operation.

- res denotes the numerical result of an operation.

2. rnd signifies the user rounding mode from MXCSR, and rz signifies the rounding mode toward

zero. (truncate), when rounding a floating-point value to an integer. For more information, refer

to Table 4-8.

3. For NAN encodings, see Table 4-3.

Table E-14. #Z - Divide-by-Zero

Instruction Condition Masked Response

Unmasked

Response and

Exception Code

DIVPS

DIVSS

DIVPD

DIVPS

src1 = finite non-zero (normal,

or denormal)

src2 = ±0

res = ±Inf,

#ZE = 1

src1, src2

unchanged;

#ZE = 1

Table E-13. #I - Invalid Operations (Contd.)

Instruction Condition Masked Response

Unmasked

Response and

Exception Code