Intel 64 and IA-32 Architectures Software Developers Manual Volume 1, Basic Architecture

Vol. 1 2-13

INTEL

64 AND IA-32 ARCHITECTURES

Intel Core 2 Extreme, Intel Core 2 Duo processors and Intel Xeon processor 5100

series implement two processor cores based on the Intel Core microarchitecture, the

functionality of the subsystems in each core are depicted in Figure 2-3.

Figure 2-3. The Intel Core Microarchitecture Pipeline Functionality

2.2.3.1 The Front End

The front end of Intel Core microarchitecture provides several enhancements to feed

the Intel Wide Dynamic Execution engine:

• Instruction fetch unit prefetches instructions into an instruction queue to

maintain steady supply of instruction to the decode units.

• Four-wide decode unit can decode 4 instructions per cycle or 5 instructions per

cycle with Macrofusion.

• Macrofusion fuses common sequence of two instructions as one decoded

instruction (micro-ops) to increase decoding throughput.

• Microfusion fuses common sequence of two micro-ops as one micro-ops to

improve retirement throughput.

Decode

ALU

Branch

MMX/SSE/FP

Move

Load

Shared L2 Cache

Up to 10.7 GB/s

FSB

Retirement Unit

(Re-Order Buffer)

L1D Cache and DTLB

Instruction Fetch and PreDecode

Instruction Queue

Rename/Alloc

ALU

FAdd

MMX/SSE

ALU

FMul

MMX/SSE

Scheduler

Micro-

code

ROM

Store